1. Field of Invention
This invention relates generally to a method for fabricating flash memory cells, and more particularly to a method for fabricating embedded flash memory cells.
2. Description of Related Art
Electrically erasable programmable read-only-memories (EEPROMs) are widely used as memory components for personal computers and electronic equipment. A conventional EEPROM memory cell comprises a floating gate transistor structure that is programmable, erasable and can store data. However, the conventional EEPROM suffers from a slow storage and retrieval time of typically around 150 ns to 200 ns. Recently, a faster EEPROM, such as a flash memory, has been developed having a storage and retrieval time of about 70 ns to 80 ns.
FIG. 1 is a top view showing a transistor memory cell structure of a conventional flash memory, wherein S represents source regions and D represents drain regions. Typically, about 16 memory cells jointly connect to an outlet contact window of the transistor memory cell. FIG. 2 is a cross-sectional view taken along line A--A of FIG. 1 depicting a memory cell of the conventional flash memory. As shown, each memory cell is actually a floating gate transistor comprising a floating gate layer 10, a controlling gate layer 12, a tunneling oxide layer 14, a drain region 16, a source region 18 and a doped source region 20.
A conventional floating gate transistor relies on hot electrons for operation. To store data into memory, high voltages of about 6V and 12V are applied to drain region 16 and controlling gate layer 12, respectively. Accordingly, hot electrons flow out from source region 18 and through tunneling oxide layer 14 near an end of drain region 16, and are injected and trapped inside floating gate layer 10, raising the threshold voltage of the floating gate transistor and storing data. To erase data from the memory, a high voltage of about 12V is applied to source region 18. The trapped electrons inside floating gate layer 10 tunnel through tunneling oxide layer 14 and release therethrough, clearing the data from memory.
Since a high voltage is applied during data erasure, source region 18 needs to be isolated by a less concentrated doped source region 20. This forms a deeply doped drain (DDD) structure that can withstand high voltage and prevent leakage current from the junction. However, fabrication of a deeply doped source region requires a drive-in process having a high temperature of about 950.degree. C. to 1000.degree. C. Hence, conventional flash memory cells cannot be manufactured using submicron or lower fabrication processes, since the high temperature requirement of the drive-in process adversely affects the properties of peripheral transistors, such as, threshold voltage V.sub.t, saturated drain current I.sub.dsat, and punch-through voltage.